(1) Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing thereof, and more particularly to a MOS transistor that has satisfactory high breakdown voltage characteristics and an on-resistance, and a method for manufacturing thereof.
(2) Description of the Related Art
In recent years, semiconductor devices, in which N channel MOS transistors and P channel MOS transistors are formed in SOI substrates, have been used for various applications. Particularly for semiconductor devices used in drive circuits in a plasma display which are required to achieve compatibility between improvement of breakdown voltage characteristics and reduction of an on-resistance, MOS transistors having an offset structure have been used.
The following describes a conventional MOS transistor having an offset structure with reference to the drawings.
FIG. 1 is a cross-sectional view showing a structure of an N channel MOS transistor described in Japanese Patent Laid-Open Application No. 2001-102586 publication.
The MOS transistor is composed of: a SOI substrate 100; a local-oxidation-of-silicon (LOCOS) film (hereafter referred to as LOCOS film) 105 that is formed on the SOI substrate 100 by a LOCOS method; a source electrode 115 and a drain electrode 121 that are made of metal; a gate electrode 116 that is made of polysilicon; and a gate oxide film 117 that is made of a thin silicon dioxide film. Note that a part of a surface of the SOI substrate 100 between the source electrode 115 and the drain electrode 121, on which the gate oxide film 117 is not formed, is covered with an insulating film (not shown in FIG. 1).
The SOI substrate 100 is made up of: a supporting substrate (silicon substrate) 101; a buried oxide film 102 that is formed on the supporting substrate 101; and an N− type semiconductor layer 103 that is formed on the buried oxide film 102.
In the semiconductor layer 103, there are formed: a P type body region 112 that is implanted with P type impurities of a low concentration; an N type drain buffer region 118 that is implanted with N type impurities of a low concentration; an N type drain well region 122 (L in FIG. 1) that is implanted with N type impurities of a low concentration; and an N+ type drain contact region 120 that is implanted with N type impurities of a high concentration.
In the P type body region 112, an N+ type source region 111 implanted with N type impurities of a high concentration and a P+ type back gate contact region 114 implanted with P type impurities of a high concentration are formed to be exposed to a surface of the semiconductor layer 103, and a P type threshold value (Vt) control diffusion layer (hereafter referred to as P type Vt control diffusion layer) 113 implanted with P type impurities of a low concentration is formed to surround the N+ type source region 111 and the P+ type back gate contact region 114. Here, the P type body region 112 is electrically connected to the N+ type source region 111 by the source electrode 115, and the P+ type back gate contact region 114 improves an electric connection status in the N+ type source region 111 and the P type body region 112.
The N type drain buffer region 118, whose end at a source side reaches below the gate electrode 116, has a diffusion region that is overlapped on the P type body region 112. On the other hand, the N type drain well region 122 does not have such a diffusion region overlapped on the P type body region 112. Furthermore, the N type drain buffer region 118 is shallower than the P type body region 112 and the N type drain well region 122, and has a diffusion region that is in contact with the semiconductor layer 103 between the P type body region 112 and the N type drain well region 122.
The LOCOS film 105 is formed on a region on the surface of the semiconductor layer 103 between the N+ type source region 111 and the N+ type drain contact region 120, and the region is near the N+ type drain contact region 120. On the other hand, the gate oxide film 117 is formed on a region on the above surface, but the region is near the N+ type source region 111. The gate electrode 116 is formed on the gate oxide film 117 and a part of the LOCOS film 105. Here, in order to reduce electric field concentration in a neighborhood of the N+ type source region 111, the gate electrode 116 is formed over the LOCOS film 105 and the gate oxide film 117, which serves as a kind of field plate.
In the MOS transistor having the above structure, the diffusion region where the P type body region 112 is overlapped with the N type drain buffer region 118 has a concentration gradient such that an N type impurity concentration is varied in a transverse direction from a source side to a drain side. Therefore, when a positive high voltage is applied to the drain electrode, an electric field concentration in the transverse direction between a drain and a source is reduced, so that a high drain-to-source breakdown voltage can be realized.
Meanwhile, in the conventional MOS transistor, when a high drain-to-source breakdown voltage is to be realized, it is necessary to lower the impurity concentration in the N type drain buffer region 118 in order not to restrain an extension of a depletion layer growing from a surface of a PN junction between the P type body region 112 and the N type drain buffer region 118. However, when the impurity concentration in the N type drain buffer region 118 is lowered, resistance in the N type drain buffer region 118 is increased especially in a part ranging from the PN junction surface between the P type body region 112 and the N type drain buffer region 118 to the N type drain well region 122 (L in FIG. 1), resulting in a significant increase of an on-resistance. Therefore, the conventional MOS transistor fails to achieve compatibility between increase of the drain-to-source breakdown voltage and reduction of the on-resistance.
In order to address the above problem, as methods to reduce the on-resistance in the MOS transistor, there is a method by which a deep drain well region is formed in the drain side region adjoining the body region. FIG. 2 is a cross-sectional view showing a structure of a MOS transistor applied with the above method. Note that dashed lines in FIG. 2 show a potential distribution in the MOS transistor when the gate electrode and the source electrode are set to 0 V, and a positive high voltage is applied to the drain electrode.
The MOS transistor shown in FIG. 2 differs from the MOS transistor shown in FIG. 1 in that there is not an N type impurity region of a shallow diffusion depth between the N+ type source region 111 and the N+ type drain contact region 120 (L in FIG. 2). In the MOS transistor shown in FIG. 2, during so-called turning-on when the source electrode is set to 0 V and positive voltages are applied to the gate electrode and the drain electrode, electrons having flowed through a channel from the source pass through a deep N type drain well region 119, so that an on-resistance is significantly reduced.
However, in the MOS transistor shown in FIG. 2, since a P type impurity concentration in the P type body region 112 is relatively low, when the source electrode and the source electrode are set to 0 V and a positive voltage is applied to the drain electrode, a depletion layer significantly extends from a boundary between the P type body region 112 and the N type drain well region 119 towards a side of the P type body region 112. Furthermore, since the gate electrode is set to 0 V, potentials are skewed towards a side of the gate electrode 116. Therefore, in the N type drain well region 119 immediately under the gate oxide film 117, the potentials are distributed in a direction perpendicular to a surface of a PN junction between the P type body region 112 and the N type drain well region 119, and the potentials are concentrated in a region including the source side end of the LOCOS film 105 (A in FIG. 2), resulting in an extreme increase of an electric field. Thus, the MOS transistor shown in FIG. 2 fails to ensure a high breakdown voltage. That is, compatibility between increase of the drain-to-source breakdown voltage and reduction of the on-resistance is not able to be achieved.
Furthermore, as other methods to increase the drain-to-source breakdown voltage in the MOS transistor, there is a method by which a distance in the transverse direction between the N+ type source region and the N+ type drain contact region is lengthened. However, this results in just enlargement of device dimensions, which causes a new problem of enlargement of chip dimensions.